The trend in IC manufacturing over the years has been to increase the number of devices (e.g., bipolar or MOS transistors, capacitors, resistors) formed within a semiconductor substrate. This increase in device integration is made possible primarily by advances in material deposition techniques (e.g., the ionized cluster beam methodology), as well as in photolithographic and etching techniques. These advances have correspondingly decreased the area on a semiconductor substrate (e.g., silicon, germanium) taken up by the active devices and the electrically-isolating areas. However, as device sizes have shrunk, problems such as uneven topography (i.e., non-planar or irregular surfaces) and inaccurate alignment of device layers have arisen. These problems, in turn, have caused a number of manufacturing process and IC operational reliability concerns.
For example, it is well-known in the art to use a local oxidation of silicon ("LOCOS") approach to electrically isolate or insulate between the active areas of a device formed in the semiconductor substrate or between the individual devices in the substrate. The LOCOS process basically comprises the initial step of placing a pad oxide layer on the substrate surface areas where the active devices are to be formed. The pad oxide layer is then typically covered by a layer of silicon nitride. The silicon nitride and pad oxide layers act as a mask or barrier to the formation of the insulating field oxide over the active device areas of the semiconductor substrate. Field oxide formation results from the controlled oxidation of the silicon substrate by which a volume expansion occurs, wherein roughly one-half of the thickness of the field oxide region is above the substrate surface and the other one-half of the field oxide thickness is below the substrate surface.
However, a field oxide region selectively formed in a silicon substrate by the LOCOS process is not without its drawbacks. One problem is the undesired lateral encroachment or extension of the field oxide into the active device areas on the substrate underneath the mask layers. This is the well-known "bird's beak" phenomenon caused, in part, by the relatively large desired thickness of the field oxide region. To achieve such a thickness, an excessive amount of oxidation time is required. Thus, there is an inherent tradeoff between field oxide width and thickness. Also, besides encroaching upon and reducing the size of the active device areas on the substrate, the "bird's beak" phenomenon can result in regions of high stresses in the field oxide, especially adjacent the abutting nitride masks.
There are numerous known attempts in the prior art to alleviate the "bird's beak" phenomenon. One proposed solution has been to use an intermediate layer of polycrystalline silicon ("polysilicon") between the pad oxide and nitride layers. The polysilicon reportedly reduces oxidation-induced stacking faults resulting from the stress caused by the different thermal coefficients of expansion between the silicon semiconductor substrate and the silicon nitride layer. The polysilicon absorbs the excessive stress caused by the silicon nitride and prevents the lateral encroachment of oxidants. See U.S. Pat. No. 4,407,696. Other known attempts to solve the "bird's beak" phenomenon involve additional, complicated processing steps, such as adding, patterning and etching of the nitride and pad oxide layers as well as the field oxide regions.
Another problem with the LOCOS approach to forming the field oxide is the resulting non-planar or irregular topography of the semiconductor substrate surface. This causes problems, for example, in the patterning and etching of overlying conductive metallization layers. Known attempts to level or planarize the substrate surface at the field oxide have unduly complicated IC processing. For example, one known approach initially forms a trench in the silicon semiconductor substrate. The trench is then filled with a deposited or thermally-grown oxide. However, forming a trench with steep side walls and sharp corners, and then filling in the trench with oxide can lead to crystalline defects in the silicon substrate. Other known leveling approaches use a spin-on-glass as the leveling layer.
Further problems with the LOCOS approach to forming the field oxide include the inherent film-thinning effect. This effect results from the fact that the thickness of the field oxide layer is greater for relatively wider isolating regions formed on the silicon substrate, as opposed to relatively narrower isolating regions. An unduly thin field oxide layer may allow implanted ions to undesirably travel completely through the field oxide layer (i.e., the "punchthrough" effect). The thin field oxide layer also increases the capacitance between an overlying conductor and the underlying silicon substrate, thereby decreasing the speed of the semiconductor device. Thinner field oxide may also reduce the field inversion voltage causing leakage between adjacent active areas.
Other problems with the LOCOS approach include the formation of undesirable nitride "spots" or regions along the interface between the silicon substrate and oxide region. Normal removal or prevention of these spots involves additional, complex manufacturing steps. Generally, any time the number of IC processing steps is increased, a higher probability occurs of creating defects in the IC. This lowers the effective yield and reliability of the ICs.
Problems of a different nature with the LOCOS approach arise when the IC is exposed to ionizing radiation, such as in a space or nuclear environment. Ionizing radiation can generate electron/hole pairs. When generated in the silicon substrate, these pairs tend to recombine rapidly, which normally is not a problem for IC device operation. However, electron/hole pairs formed in an oxide region are more problematic. This is because, in oxide, electrons are relatively more mobile than holes. The electrons may become separated from the holes, making recombination difficult, and resulting in a parasitic leakage current due to early onset of field inversion facilitated by hole trapping.
This radiation-induced, parasitic leakage current may be categorized as either device-to-device or drain-to-source leakage. Device-to-device leakage current is due to positive trapped charge in the field oxide, which causes an inversion of the P-type doped silicon separating the N-type doped source and drain regions of two N-channel transistors. On the other hand, drain-to-source leakage current results from inversion of the P-type doped silicon along the field oxide edge of a single transistor formed in the semiconductor substrate.
In an attempt to alleviate these leakage currents, it is known to implant the field oxide region, either before or after its formation, with a boron impurity. The amount of implanted dopant is calculated to prevent the formation of parasitic transistors. However, with the traditional LOCOS field oxide dopant implant process, a dopant depletion exists at the interface and extending down into the semiconductor substrate. Ideally, there is a higher impurity concentration at the substrate surface. Also, the total dose radiation hardening characteristics of LOCOS field oxide are relatively poor.
Known attempts to more uniformly deposit a planar oxide, instead of a localized field oxide, have introduced an additional problem with the resulting oxide topography. More specifically, the resulting steep vertical oxide sidewalls make subsequent processing of the multi-level interconnect metallization difficult.